Implementation and Design of Reversible Logic Based Carry Tree Adders

Abstract

Parallel prefix adders excel in reducing delays in VLSI circuits. This work describes three reversible versions: the Brent-Kung Adder, the tree-spanning Adder, and the Kogge Stone Adder. The designs in question have been recreated and produced on a Xilinx 14.3 platform with Verilog High-Definition Layout software. In comparison with typical carry-lookahead adders, the suggested reversible parallel prefix adders provide large latency savings while maintaining energy consumption and area. Reversible logic has emerged as a possible option to meet the rising demand for cost-effective processing, especially in the areas of quantum computing, inexpensively VLSI design, and nanotechnology. This work describes the design and implementation of bidirectional logicbased carry tree adders (CTAs), which are significantly more power efficient and faster than ordinary adders. The suggested CTA architecture uses reversible gates like as the Toffoli, Fredkin, and Peres gates to ensure minimum information loss, possibly decreasing power consumption to zero. The carry tree's orderly arrangement reduces carry propagated time, allowing for quicker calculations. A complete design approach is demonstrated by building a 4-bit reversible CTA, which includes circuit designs and gate combinations.